Thursday, 14 April 2016

M.Tech I-II (VLSI & ES) 1st Mid Examination

This is to inform all the M.Tech - I Year II Semester (VLSI & ES) students that I-MID Examinations will commence from 18/04/2016(Monday). The detailed timetable is given below:
VLSI SYSTEM DESIGN:

  1. Low Power VLSI Design - 18/04/2016 - 10:00AM to 12:00PM
  2. Design for Testability - 19/04/2016 - 10:00AM to 12:00PM
  3. CMOS Mixed Signal Circuit Design - 20/04/2016 - 10:00AM to 12:00PM
  4. System on Chip Architecture - 21/04/2016 - 10:00AM to 12:00PM
  5. VLSI & DSPA - 22/04/2016 - 10:00AM to 12:00PM
  6. Scripting Languages - 23/04/2016 - 10:00AM to 12:00PM

EMBEDDED SYSTEMS:

  1. DSPA - 18/04/2016 - 10:00AM to 12:00PM
  2. Embedded Networking - 19/04/2016 - 10:00AM to 12:00PM
  3. Sensors and Actuators - 20/04/2016 - 10:00AM to 12:00PM
  4. System on Chip Architecture - 21/04/2016 - 10:00AM to 12:00PM
  5. HSCD - 22/04/2016 - 10:00AM to 12:00PM
  6. AWSN - 23/04/2016 - 10:00AM to 12:00PM

This Project is Designed & Developed by Venkata Bommineni
Contact Number: 9704041508, 8106604242, 9292955581
Maintained by Manohar Reddy , Shanthan Kumar & A S Bruhadroop