| Hallticket No | Subject Name | Internal Marks | External Marks | Total Marks | Credits |
| 12R11D5701 | SYSTEM ON CHIP ARCHITECTURE | 39 | 38 | 77 | 1 |
| 12R11D5701 | CMOS ANALOG & MIXED SIGNAL DESIGN | 38 | 33 | 71 | 1 |
| 12R11D5701 | EMBEDDED REAL TIME OPERATING SYSTEMS | 38 | 42 | 80 | 1 |
| 12R11D5701 | DESIGN OF FAULT TOLERANT SYSTEMS | 38 | 33 | 71 | 1 |
| 12R11D5701 | IMAGE & VIDEO PROCESSING | 37 | 45 | 82 | 1 |
| 12R11D5701 | LOW POWER VLSI DESIGN | 38 | 37 | 75 | 1 |
| 12R11D5701 | EMBEDDED SYSTEMS DESIGN LAB | 36 | 54 | 90 | 1 |
| 12R11D5701 | SEMINAR - II | 44 | 0 | 44 | 1 |
| 12R11D5702 | SYSTEM ON CHIP ARCHITECTURE | 31 | 29 | 60 | 1 |
| 12R11D5702 | CMOS ANALOG & MIXED SIGNAL DESIGN | 27 | 14 | 41 | 0 |
| 12R11D5702 | EMBEDDED REAL TIME OPERATING SYSTEMS | 26 | -1 | 26 | 0 |
| 12R11D5702 | DESIGN OF FAULT TOLERANT SYSTEMS | 23 | -1 | 23 | 0 |
| 12R11D5702 | IMAGE & VIDEO PROCESSING | 32 | 29 | 61 | 1 |
| 12R11D5702 | LOW POWER VLSI DESIGN | 27 | -1 | 27 | 0 |
| 12R11D5702 | EMBEDDED SYSTEMS DESIGN LAB | 28 | 50 | 78 | 1 |
| 12R11D5702 | SEMINAR - II | 40 | 0 | 40 | 1 |
| 12R11D5703 | SYSTEM ON CHIP ARCHITECTURE | 34 | 29 | 63 | 1 |
| 12R11D5703 | CMOS ANALOG & MIXED SIGNAL DESIGN | 37 | 25 | 62 | 1 |
| 12R11D5703 | EMBEDDED REAL TIME OPERATING SYSTEMS | 38 | 34 | 72 | 1 |
| 12R11D5703 | DESIGN OF FAULT TOLERANT SYSTEMS | 34 | 13 | 47 | 0 |
| 12R11D5703 | IMAGE & VIDEO PROCESSING | 37 | 27 | 64 | 1 |
| 12R11D5703 | LOW POWER VLSI DESIGN | 35 | 24 | 59 | 1 |
| 12R11D5703 | EMBEDDED SYSTEMS DESIGN LAB | 35 | 55 | 90 | 1 |
| 12R11D5703 | SEMINAR - II | 45 | 0 | 45 | 1 |
| 12R11D5704 | SYSTEM ON CHIP ARCHITECTURE | 32 | 33 | 65 | 1 |
| 12R11D5704 | CMOS ANALOG & MIXED SIGNAL DESIGN | 28 | 24 | 52 | 1 |
| 12R11D5704 | EMBEDDED REAL TIME OPERATING SYSTEMS | 33 | 27 | 60 | 1 |
| 12R11D5704 | DESIGN OF FAULT TOLERANT SYSTEMS | 21 | 26 | 47 | 0 |
| 12R11D5704 | IMAGE & VIDEO PROCESSING | 34 | 31 | 65 | 1 |
| 12R11D5704 | LOW POWER VLSI DESIGN | 28 | 28 | 56 | 1 |
| 12R11D5704 | EMBEDDED SYSTEMS DESIGN LAB | 29 | 51 | 80 | 1 |
| 12R11D5704 | SEMINAR - II | 40 | 0 | 40 | 1 |
| 12R11D5705 | SYSTEM ON CHIP ARCHITECTURE | 39 | 33 | 72 | 1 |
| 12R11D5705 | CMOS ANALOG & MIXED SIGNAL DESIGN | 38 | 27 | 65 | 1 |
| 12R11D5705 | EMBEDDED REAL TIME OPERATING SYSTEMS | 38 | 43 | 81 | 1 |
| 12R11D5705 | DESIGN OF FAULT TOLERANT SYSTEMS | 40 | 36 | 76 | 1 |
| 12R11D5705 | IMAGE & VIDEO PROCESSING | 38 | 49 | 87 | 1 |
| 12R11D5705 | LOW POWER VLSI DESIGN | 38 | 28 | 66 | 1 |
| 12R11D5705 | EMBEDDED SYSTEMS DESIGN LAB | 38 | 57 | 95 | 1 |
| 12R11D5705 | SEMINAR - II | 46 | 0 | 46 | 1 |
| 12R11D5706 | SYSTEM ON CHIP ARCHITECTURE | 35 | 36 | 71 | 1 |
| 12R11D5706 | CMOS ANALOG & MIXED SIGNAL DESIGN | 37 | 34 | 71 | 1 |
| 12R11D5706 | EMBEDDED REAL TIME OPERATING SYSTEMS | 38 | 41 | 79 | 1 |
| 12R11D5706 | DESIGN OF FAULT TOLERANT SYSTEMS | 32 | 37 | 69 | 1 |
| 12R11D5706 | IMAGE & VIDEO PROCESSING | 38 | 48 | 86 | 1 |
| 12R11D5706 | LOW POWER VLSI DESIGN | 37 | 30 | 67 | 1 |
| 12R11D5706 | EMBEDDED SYSTEMS DESIGN LAB | 37 | 56 | 93 | 1 |
| 12R11D5706 | SEMINAR - II | 47 | 0 | 47 | 1 |
| 12R11D5707 | SYSTEM ON CHIP ARCHITECTURE | 26 | 32 | 58 | 1 |
| 12R11D5707 | CMOS ANALOG & MIXED SIGNAL DESIGN | 26 | 33 | 59 | 1 |
| 12R11D5707 | EMBEDDED REAL TIME OPERATING SYSTEMS | 34 | 34 | 68 | 1 |
| 12R11D5707 | DESIGN OF FAULT TOLERANT SYSTEMS | 26 | 32 | 58 | 1 |
| 12R11D5707 | IMAGE & VIDEO PROCESSING | 26 | 43 | 69 | 1 |
| 12R11D5707 | LOW POWER VLSI DESIGN | 27 | 24 | 51 | 1 |
| 12R11D5707 | EMBEDDED SYSTEMS DESIGN LAB | 32 | 53 | 85 | 1 |
| 12R11D5707 | SEMINAR - II | 43 | 0 | 43 | 1 |
| 12R11D5708 | SYSTEM ON CHIP ARCHITECTURE | 39 | 36 | 75 | 1 |
| 12R11D5708 | CMOS ANALOG & MIXED SIGNAL DESIGN | 40 | 33 | 73 | 1 |
| 12R11D5708 | EMBEDDED REAL TIME OPERATING SYSTEMS | 40 | 48 | 88 | 1 |
| 12R11D5708 | DESIGN OF FAULT TOLERANT SYSTEMS | 39 | 32 | 71 | 1 |
| 12R11D5708 | IMAGE & VIDEO PROCESSING | 40 | 57 | 97 | 1 |
| 12R11D5708 | LOW POWER VLSI DESIGN | 40 | 29 | 69 | 1 |
| 12R11D5708 | EMBEDDED SYSTEMS DESIGN LAB | 40 | 59 | 99 | 1 |
| 12R11D5708 | SEMINAR - II | 48 | 0 | 48 | 1 |
| 12R11D5709 | SYSTEM ON CHIP ARCHITECTURE | 33 | 34 | 67 | 1 |
| 12R11D5709 | CMOS ANALOG & MIXED SIGNAL DESIGN | 37 | 33 | 70 | 1 |
| 12R11D5709 | EMBEDDED REAL TIME OPERATING SYSTEMS | 35 | 35 | 70 | 1 |
| 12R11D5709 | DESIGN OF FAULT TOLERANT SYSTEMS | 27 | 28 | 55 | 1 |
| 12R11D5709 | IMAGE & VIDEO PROCESSING | 35 | 41 | 76 | 1 |
| 12R11D5709 | LOW POWER VLSI DESIGN | 37 | 24 | 61 | 1 |
| 12R11D5709 | EMBEDDED SYSTEMS DESIGN LAB | 36 | 52 | 88 | 1 |
| 12R11D5709 | SEMINAR - II | 45 | 0 | 45 | 1 |
| 12R11D5710 | SYSTEM ON CHIP ARCHITECTURE | 36 | 38 | 74 | 1 |
| 12R11D5710 | CMOS ANALOG & MIXED SIGNAL DESIGN | 39 | 39 | 78 | 1 |
| 12R11D5710 | EMBEDDED REAL TIME OPERATING SYSTEMS | 40 | 40 | 80 | 1 |
| 12R11D5710 | DESIGN OF FAULT TOLERANT SYSTEMS | 30 | 36 | 66 | 1 |
| 12R11D5710 | IMAGE & VIDEO PROCESSING | 39 | 54 | 93 | 1 |
| 12R11D5710 | LOW POWER VLSI DESIGN | 39 | 40 | 79 | 1 |
| 12R11D5710 | EMBEDDED SYSTEMS DESIGN LAB | 39 | 59 | 98 | 1 |
| 12R11D5710 | SEMINAR - II | 48 | 0 | 48 | 1 |
| 12R11D5711 | SYSTEM ON CHIP ARCHITECTURE | 37 | 33 | 70 | 1 |
| 12R11D5711 | CMOS ANALOG & MIXED SIGNAL DESIGN | 40 | 24 | 64 | 1 |
| 12R11D5711 | EMBEDDED REAL TIME OPERATING SYSTEMS | 39 | 44 | 83 | 1 |
| 12R11D5711 | DESIGN OF FAULT TOLERANT SYSTEMS | 37 | 34 | 71 | 1 |
| 12R11D5711 | IMAGE & VIDEO PROCESSING | 40 | 59 | 99 | 1 |
| 12R11D5711 | LOW POWER VLSI DESIGN | 40 | 39 | 79 | 1 |
| 12R11D5711 | EMBEDDED SYSTEMS DESIGN LAB | 38 | 59 | 97 | 1 |
| 12R11D5711 | SEMINAR - II | 48 | 0 | 48 | 1 |
| 12R11D5712 | SYSTEM ON CHIP ARCHITECTURE | 35 | 36 | 71 | 1 |
| 12R11D5712 | CMOS ANALOG & MIXED SIGNAL DESIGN | 37 | 24 | 61 | 1 |
| 12R11D5712 | EMBEDDED REAL TIME OPERATING SYSTEMS | 37 | 36 | 73 | 1 |
| 12R11D5712 | DESIGN OF FAULT TOLERANT SYSTEMS | 31 | 34 | 65 | 1 |
| 12R11D5712 | IMAGE & VIDEO PROCESSING | 35 | 45 | 80 | 1 |
| 12R11D5712 | LOW POWER VLSI DESIGN | 38 | 24 | 62 | 1 |
| 12R11D5712 | EMBEDDED SYSTEMS DESIGN LAB | 35 | 57 | 92 | 1 |
| 12R11D5712 | SEMINAR - II | 45 | 0 | 45 | 1 |