Friday 3 January 2014

55-M.Tech. II Semester (R09) Regular


Hallticket No Subject Name Internal Marks External Marks Total Marks Credits
10R11D5507 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 20 18 38 0
11R11D5512 LOW POWER VLSI DESIGN 22 -1 22 0
12R11D5501 HARDWARE SOFTWARE CO-DESIGN 38 42 80 1
12R11D5501 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 39 40 79 1
12R11D5501 SYSTEM MODELING AND SIMULATION 40 40 80 1
12R11D5501 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 38 54 92 1
12R11D5501 LOW POWER VLSI DESIGN 39 36 75 1
12R11D5501 SYSTEM ON CHIP ARCHITECTURE 37 39 76 1
12R11D5501 EMBEDDED SYSTEMS LAB - II USING PSOC 40 58 98 1
12R11D5501 SEMINAR - II 48 0 48 1
12R11D5502 HARDWARE SOFTWARE CO-DESIGN 35 44 79 1
12R11D5502 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 39 33 72 1
12R11D5502 SYSTEM MODELING AND SIMULATION 38 47 85 1
12R11D5502 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 36 53 89 1
12R11D5502 LOW POWER VLSI DESIGN 40 40 80 1
12R11D5502 SYSTEM ON CHIP ARCHITECTURE 33 42 75 1
12R11D5502 EMBEDDED SYSTEMS LAB - II USING PSOC 39 57 96 1
12R11D5502 SEMINAR - II 46 0 46 1
12R11D5503 HARDWARE SOFTWARE CO-DESIGN 33 40 73 1
12R11D5503 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 37 36 73 1
12R11D5503 SYSTEM MODELING AND SIMULATION 37 34 71 1
12R11D5503 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 34 46 80 1
12R11D5503 LOW POWER VLSI DESIGN 38 30 68 1
12R11D5503 SYSTEM ON CHIP ARCHITECTURE 32 33 65 1
12R11D5503 EMBEDDED SYSTEMS LAB - II USING PSOC 37 55 92 1
12R11D5503 SEMINAR - II 44 0 44 1
12R11D5504 HARDWARE SOFTWARE CO-DESIGN 32 38 70 1
12R11D5504 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 34 35 69 1
12R11D5504 SYSTEM MODELING AND SIMULATION 36 36 72 1
12R11D5504 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 19 46 65 1
12R11D5504 LOW POWER VLSI DESIGN 35 31 66 1
12R11D5504 SYSTEM ON CHIP ARCHITECTURE 31 43 74 1
12R11D5504 EMBEDDED SYSTEMS LAB - II USING PSOC 35 54 89 1
12R11D5504 SEMINAR - II 42 0 42 1
12R11D5505 HARDWARE SOFTWARE CO-DESIGN 34 27 61 1
12R11D5505 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 32 24 56 1
12R11D5505 SYSTEM MODELING AND SIMULATION 36 28 64 1
12R11D5505 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 23 43 66 1
12R11D5505 LOW POWER VLSI DESIGN 33 29 62 1
12R11D5505 SYSTEM ON CHIP ARCHITECTURE 31 31 62 1
12R11D5505 EMBEDDED SYSTEMS LAB - II USING PSOC 35 52 87 1
12R11D5505 SEMINAR - II 42 0 42 1
12R11D5506 HARDWARE SOFTWARE CO-DESIGN 35 40 75 1
12R11D5506 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 40 49 89 1
12R11D5506 SYSTEM MODELING AND SIMULATION 37 45 82 1
12R11D5506 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 35 47 82 1
12R11D5506 LOW POWER VLSI DESIGN 36 39 75 1
12R11D5506 SYSTEM ON CHIP ARCHITECTURE 37 45 82 1
12R11D5506 EMBEDDED SYSTEMS LAB - II USING PSOC 36 53 89 1
12R11D5506 SEMINAR - II 43 0 43 1
12R11D5507 HARDWARE SOFTWARE CO-DESIGN 26 28 54 1
12R11D5507 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 26 43 69 1
12R11D5507 SYSTEM MODELING AND SIMULATION 26 35 61 1
12R11D5507 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 20 39 59 1
12R11D5507 LOW POWER VLSI DESIGN 31 19 50 0
12R11D5507 SYSTEM ON CHIP ARCHITECTURE 26 12 38 0
12R11D5507 EMBEDDED SYSTEMS LAB - II USING PSOC 34 50 84 1
12R11D5507 SEMINAR - II 40 0 40 1
12R11D5508 HARDWARE SOFTWARE CO-DESIGN 34 39 73 1
12R11D5508 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 37 35 72 1
12R11D5508 SYSTEM MODELING AND SIMULATION 36 33 69 1
12R11D5508 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 28 36 64 1
12R11D5508 LOW POWER VLSI DESIGN 35 33 68 1
12R11D5508 SYSTEM ON CHIP ARCHITECTURE 31 32 63 1
12R11D5508 EMBEDDED SYSTEMS LAB - II USING PSOC 37 54 91 1
12R11D5508 SEMINAR - II 44 0 44 1
12R11D5509 HARDWARE SOFTWARE CO-DESIGN 0 -1 0 0
12R11D5509 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 0 -1 0 0
12R11D5509 SYSTEM MODELING AND SIMULATION 0 -1 0 0
12R11D5509 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 0 -1 0 0
12R11D5509 LOW POWER VLSI DESIGN 0 -1 0 0
12R11D5509 SYSTEM ON CHIP ARCHITECTURE 0 -1 0 0
12R11D5509 EMBEDDED SYSTEMS LAB - II USING PSOC 0 -1 0 0
12R11D5509 SEMINAR - II 0 0 0 0
12R11D5510 HARDWARE SOFTWARE CO-DESIGN 32 33 65 1
12R11D5510 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 35 40 75 1
12R11D5510 SYSTEM MODELING AND SIMULATION 33 36 69 1
12R11D5510 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 26 50 76 1
12R11D5510 LOW POWER VLSI DESIGN 31 28 59 1
12R11D5510 SYSTEM ON CHIP ARCHITECTURE 32 33 65 1
12R11D5510 EMBEDDED SYSTEMS LAB - II USING PSOC 34 51 85 1
12R11D5510 SEMINAR - II 41 0 41 1
12R11D5511 HARDWARE SOFTWARE CO-DESIGN 32 31 63 1
12R11D5511 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 31 24 55 1
12R11D5511 SYSTEM MODELING AND SIMULATION 36 21 57 0
12R11D5511 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 24 27 51 1
12R11D5511 LOW POWER VLSI DESIGN 31 21 52 0
12R11D5511 SYSTEM ON CHIP ARCHITECTURE 31 18 49 0
12R11D5511 EMBEDDED SYSTEMS LAB - II USING PSOC 36 54 90 1
12R11D5511 SEMINAR - II 42 0 42 1
12R11D5512 HARDWARE SOFTWARE CO-DESIGN 31 24 55 1
12R11D5512 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 35 28 63 1
12R11D5512 SYSTEM MODELING AND SIMULATION 37 28 65 1
12R11D5512 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 26 49 75 1
12R11D5512 LOW POWER VLSI DESIGN 32 29 61 1
12R11D5512 SYSTEM ON CHIP ARCHITECTURE 26 29 55 1
12R11D5512 EMBEDDED SYSTEMS LAB - II USING PSOC 35 53 88 1
12R11D5512 SEMINAR - II 43 0 43 1
12R11D5513 HARDWARE SOFTWARE CO-DESIGN 34 31 65 1
12R11D5513 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 36 31 67 1
12R11D5513 SYSTEM MODELING AND SIMULATION 37 31 68 1
12R11D5513 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 26 44 70 1
12R11D5513 LOW POWER VLSI DESIGN 35 24 59 1
12R11D5513 SYSTEM ON CHIP ARCHITECTURE 35 26 61 1
12R11D5513 EMBEDDED SYSTEMS LAB - II USING PSOC 36 52 88 1
12R11D5513 SEMINAR - II 44 0 44 1
12R11D5514 HARDWARE SOFTWARE CO-DESIGN 26 48 74 1
12R11D5514 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 26 40 66 1
12R11D5514 SYSTEM MODELING AND SIMULATION 26 42 68 1
12R11D5514 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 26 58 84 1
12R11D5514 LOW POWER VLSI DESIGN 26 38 64 1
12R11D5514 SYSTEM ON CHIP ARCHITECTURE 26 39 65 1
12R11D5514 EMBEDDED SYSTEMS LAB - II USING PSOC 35 53 88 1
12R11D5514 SEMINAR - II 44 0 44 1
12R11D5515 HARDWARE SOFTWARE CO-DESIGN 34 38 72 1
12R11D5515 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 35 35 70 1
12R11D5515 SYSTEM MODELING AND SIMULATION 35 31 66 1
12R11D5515 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 30 18 48 0
12R11D5515 LOW POWER VLSI DESIGN 36 29 65 1
12R11D5515 SYSTEM ON CHIP ARCHITECTURE 32 33 65 1
12R11D5515 EMBEDDED SYSTEMS LAB - II USING PSOC 34 50 84 1
12R11D5515 SEMINAR - II 42 0 42 1
12R11D5516 HARDWARE SOFTWARE CO-DESIGN 37 32 69 1
12R11D5516 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 38 33 71 1
12R11D5516 SYSTEM MODELING AND SIMULATION 35 34 69 1
12R11D5516 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 35 45 80 1
12R11D5516 LOW POWER VLSI DESIGN 39 37 76 1
12R11D5516 SYSTEM ON CHIP ARCHITECTURE 34 34 68 1
12R11D5516 EMBEDDED SYSTEMS LAB - II USING PSOC 35 51 86 1
12R11D5516 SEMINAR - II 45 0 45 1
12R11D5517 HARDWARE SOFTWARE CO-DESIGN 36 38 74 1
12R11D5517 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES 38 40 78 1
12R11D5517 SYSTEM MODELING AND SIMULATION 38 39 77 1
12R11D5517 CPLD & FPGA ARCHITECTURES AND APPLICATIONS 33 31 64 1
12R11D5517 LOW POWER VLSI DESIGN 37 19 56 0
12R11D5517 SYSTEM ON CHIP ARCHITECTURE 32 40 72 1
12R11D5517 EMBEDDED SYSTEMS LAB - II USING PSOC 38 56 94 1
12R11D5517 SEMINAR - II 46 0 46 1

This Project is Designed & Developed by Venkata Bommineni
Contact Number: 8106604242
Maintained by Shanthan Kumar